(1) Field of the Invention
The present invention relates generally to a method of manufacturing a non-volatile memory cell, and more particularly, to a method of forming a non-volatile memory cell having a floating gate with sharp corners.
(2) Description of the Related Art
Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. The ULSI circuits are generally composed of complementary metal oxide semiconductor field effect transistors (MOSFETs). For a typical random access memory (RAM), the data stored in the memory is volatile. For this reason, a power supply is needed to refresh the data stored in the memory.
On the other hand, non-volatile memories such as Read-only-memories (ROMs), electrically erasable programmable ROM (EEPEOM) or flash memories, are memories into which information is permanently stored.
In order to reduce the production cost and enhance the manufacture yield of a non-volatile memory device, it is important to develop a single-transistor electrically programmable and erasable memory device. For this reason, a method for forming a single transistor non-volatile electrically alterable semiconductor memory device was disclosed in U.S. Pat. No. 5,029,130. According to this prior art, referring first to FIG. 1A, a first insulating layer 12 is formed on a silicon substrate 10. Thereafter, a polysilicon layer 14 and a silicon nitride layer 16 are formed on the first insulating layer 12. After that, the silicon nitride layer 16 is next patterned by performing conventional photolithographic and etching process to form an opening 18.
Referring now to FIG. 1B, a thermal oxidation process is performed to form an oxide layer 20 in the opening 18. As shown in FIG. 1B, the silicon nitride layer 16 is partially lifted during the thermal oxidation process because of the bird""s beak effect. Next, the silicon nitride layer 16 is removed by performing a wet etching process, as shown in FIG. 1C.
Referring now to FIG. 1D, an anisotropic etching process is applied to selectively etch the exposed polysilicon layer 14 which is not directly beneath the oxide layer 20. A floating gate 22 with sharp curved-up portion is thus formed, as shown in FIG. 1D.
Referring now to FIG. 1E, a thermal oxide layer 24 is grown to a certain thickness over the floating gate 22. Thereafter, nitridization of the oxide layer 24 is performed by thermally annealing the oxide layer 24 with dilute NH3 using N2 or Ar as a carrier gas at an elevated temperature; e.g., greater than 800xc2x0 C. This will result in the formation of an oxynitride film. Finally, a second polysilicon layer 26 is deposited over the oxynitride layer 24. The second polysilicon layer 26 is going to be patterned to form the control gate of the non-volatile memory cell.
According to this prior art, with a sharply defined charge injection edge, the tunneling probability of electrons between the floating gate and the control gate is at the highest. This results in a floating gate having a well-defined charge injection edge to cause tunneling of charges from the floating gate to control gate.
Accordingly, it is a primary object of the present invention to a method of forming a non-volatile memory cell having a floating gate with sharp corners.
It is another object of the present invention to provide a non-volatile memory cell with a floating gate having sharp corners.
It is further another object of the present invention to provide a method of forming a gate structure with sharp corners.
A method of forming a non-volatile memory cell having a floating gate with sharp corners is disclosed. First, a first dielectric layer and a first silicon layer are formed on a semiconductor substrate. An etching stop layer is next formed on the first silicon layer. After patterning the etching stop layer to form an opening, a dish-shaped hole is formed by performing an isotropic etching process to partially etch the first silicon layer through the opening. In one embodiment of the present invention, the isotropic etching process is performed by a wet etching process using a mixture solution of nitric acid and hydrofluoric acid as etchant. In another embodiment of the present invention, the isotropic etching process is performed by a dry etching process using Cl2 as etchant.
After removing the etching stop layer, a second dielectric layer is formed to refill the dish-shaped hole. After that, a dielectric stud is formed by performing a planarization process such as CMP to remove a portion of the second dielectric layer outside the dish-shaped hole. Thereafter, a floating gate with sharp corners is formed by performing an anisotropical etching process to etch an exposed portion of the first silicon layer using the dielectric stud as an etching mask. After removing the dielectric stud by performing a wet etching process, a tunneling dielectric layer is formed over the floating gate. Finally, a control gate of the non-volatile memory cell is formed on the tunneling dielectric layer and the first dielectric layer.